1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a magnetic random access memory device having an array of magnetic memory cells.
2. Description of the Related Art
A magnetic random access memory device having an array of magnetic memory cells has been known as one of the non-volatile semiconductor memory devices. The magnetic random access memory device has an array of magnetic memory cells, which is which comprises a magnetoresistance element. The magnetic random access memory device will hereinafter referred to as MRAM device. FIG. 1A is a schematic perspective view illustrative of one of conventional magnetoresistance elements serving as magnetic memory cells of the MRAM device. FIG. 1B is a schematic perspective view illustrative of read out operation of the magnetoresistance element of FIG. 1A. FIG. 1C is a plan view illustrative of respective magnetization states depending on stored data of the magnetoresistance element of FIG. 1A.
The single magnetic memory cell comprises a first wiring layer 11, a pinned layer 12, a non-magnetic layer 13, a free layer 14, and a second wiring layer 12. The magnetoresistance element comprises the pinned layer 12, the non-magnetic layer 13, and the free layer 14, wherein the non-magnetic layer 13 is sandwiched between the pinned layer 12 and the free layer 14. The pinned layer 12 is in contact with the first wiring layer 11. The free layer 14 is in contact with the second wiring layer 12. The pinned layer 12 and the free layer 14 are made of ferromagnetic materials. The non-magnetic layer 13 is made of an insulating material. The pinned layer 12 has a thickness of about =B 20 =l nanometers. The pinned layer 12 has a fixed magnetization direction. The non-magnetic layer 13 has a thickness of about 1.5 nanonmeters. The free layer 14 has a thickness of about 20 nanometers. The free layer 14 has a freely changeable magnetization direction.
The magnetization direction of the free layer 14 indicates stored data. The free layer 14 serves as a data storage layer. The first wiring layer 11 and the second wiring layer 15 extend in directions perpendicular to each other. The magnetoresistanice element is positioned at a crossing point between the first wiring layer 11 and the second wiring layer 15. A current 16 flows from the first wiring layer 11 through the pinned layer 12, the non-magnetic layer 13 and the free layer 14 to the second wiring layer 15. The magnetic memory cell is capable of storing binary digit data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. If the magnetization directions of the pinned layer 12 and the free layer 14 are parallel to each other, then this means that the magnetic memory cell stores a first one of binary digits, for example, data xe2x80x9c0xe2x80x9d. If the magnetization directions of the pinned layer 12 and the free layer 14 are anti-parallel to each other, then this means that the magnetic memory cell stores a first one of binary digits, for example, data xe2x80x9c1xe2x80x9d. The magnetization direction of the free layer 14 is changed depending on an externally applied magnetic field.
An electrical resistance of the non-magnetic layer 13 varies by about 10-40% due to the tunneling magnetoresistance effect between in a first state where the magnetization directions of the pinned layer 12 and the free layer 14 arc parallel to each other and a second state where the magnetization directions of the pinned layer 12 and the free layer 14 are anti-parallel to each other. A predetermined potential difference or a predetermined voltage is given to the first and second wiring layers 11 and 15 to apply a tunneling current from the pinned layer 12 through the non-magnetic layer 13 to the free layer 14. This tunneling current varies depending on the variable electrical resistance of the non-magnetic layer 13 due to the tunneling magnetoresistance effect. The data can be fetched from the magnetic memory cell by detecting the variation in the tunneling current.
The use of the tunneling magnetoresistance effect for the magnetic memory cell is more advantageous for a highly dense MRAM than a conventional giant magnetoresistance effect because a lead electrode structure of the magnetic memory cell comprising the tunneling magnetoresistance element is more simple than the magnetic memory cell comprising the giant magnetoresistance clement.
FIG. 2A is a fragmentary schematic perspective view illustrative of an array of magnetic memory cells of the MRAM of FIG. 1A. FIG. 2B is a fragmentary schematic perspective view illustrative of the array of the magnetic memory cells in write operation in FIG. 2A.
The first wiring layers 11 extend in parallel to each other in a first direction. The second wiring layers 15 extend in parallel to each other in a second direction perpendicular to the first direction. The single first wiring layer 11 and the single second wiring layer 15 has a single crossing point, where a single magnetic memory cell xe2x80x9cCxe2x80x9d is provided. The plural first wiring layers 11 and the plural second wiring layers 15 have an array of crossing points where plural magnetic memory cells xe2x80x9cCxe2x80x9d are provided. The first wiring layers 11 serve as word lines. The second wiring layers 15 serve as bit lines. One of the plural magnetic memory cells xe2x80x9cCxe2x80x9d is selected by selecting one of the word lines and one of the bit lines, for read or write operations to the selected magnetic memory cell xe2x80x9cCxe2x80x9d.
Japanese laid-open patent publication No. 2000-82791 also discloses another MRAM, wherein magnetic tunneling junction devices are used as magnetic memory cells.
The MRAM has the array of the magnetic memory cells, each of which comprises the tunneling magnetoresistance element utilizing the tunneling magnetoresistance effect, wherein the tunneling magnetoresistance element includes an insulating thin film sandwiched between the at least two ferromagnetic thin films. The tunneling magnetoresistance element is switched between a first state that the magnetization directions of the two ferromagnetic thin films are parallel to each other and a second state that the magnetization directions of the two ferromagnetic thin films are anti-parallel to each other. The resistance of the insulating film, that the tunneling current senses, is different in between the first and second states. These two states correspond to binary digits, for example, the first state corresponds to the data xe2x80x9c0xe2x80x9d and the second state corresponds to the data xe2x80x9c1xe2x80x9d.
The write operation is accomplished as follows. One of the word lines 11 and one of the bit lines 15 are selected. A first write current Isw is applied to the selected word line 11s. A first magnetic field Msw is generated around the relected word line 11s. The first write current Isw has a predetermined current value and a predetermined direction. A second write current Isb is applied to the selected bit line 15s. The second write current Isb has a predetermined current value and a predetermined direction. A second magnetic field Msb is generated around the selected bit line 15s. As a result, a superimposed magnetic field of both the first and second magnetic field Msw and Msb is applied to the crossing point of the selected word line 11s and the selected bit line 15s. The selected magnetic memory cell xe2x80x9cCsxe2x80x9d is positioned at the crossing point of the selected word line 11s and the selected bit line 15s, for which reason the selected magnetic memory cell xe2x80x9cCsxe2x80x9d is applied with the superimposed magnetic field. The free layer of the selected magnetic memory cell xe2x80x9cCsxe2x80x9d is also applied with the superimposed magnetic field, whereby magnetic domains of the free layer become ordered in a first direction, for example, in a direction parallel to the magnetization direction of the pinned layer. As a result, the selected magnetic memory cell xe2x80x9cCsxe2x80x9d stores a binary digit data xe2x80x9c0xe2x80x9d.
Any one of the first write current Isw and the second write current Isb changes its current direction to an opposite direction, whereby the direction of the magnetic field is inverted, and the direction of the superimposed magnetic field is changed by 90 degrees. As a result, the magnetic domains of the free layer become ordered in a second direction, for example, in a direction anti-parallel to the magnetization direction of the pinned layer. As a result, the selected magnetic memory cell xe2x80x9cCsxe2x80x9d stores another binary digit data xe2x80x9c1xe2x80x9d.
The read operation is accomplished as follows. One of the word lines 11 and one of the bit lines 15 arc selected. A potential difference is given to between the selected word line 11s and the selected bit line 15s for measuring a current value to detect a resistance value of the selected memory cell xe2x80x9cCsxe2x80x9d to the tunneling current. Namely, a predetermined potential difference or a predetermined voltage is given to the selected word line 11s and the selected bit line 15s to apply a tunneling current from the pinned layer through the insulating layer to the free layer of the selected memory cell xe2x80x9cCsxe2x80x9d. This tunneling current varies depending on the variable electrical resistance of the insulating layer due to the tunneling magnetoresistance effect. The binary digit data can be detected from the selected memory cell xe2x80x9cCsxe2x80x9d by detecting the variation in the tunneling current.
FIG. 3 is a diagram illustrative of a conventional array structure of the magnetic memory cells in the MRAM. An array 21 includes 2m of word lines W1, W2, W3, - - - Wm, Wm+1, - - - , and W2m, and 2n of bit lines B1, B2, B3, - - - Bn, Bn+1, - - - , B2n, as well as 2mxc3x972n of magnetic memory cells C11, C12, - - - , C2m2n which are positioned at crossing points of the word and bit lines. A word line Wi and a bit line Bj are selected to select a magnetic memory cell Cij positioned at the crossing point between the selected word line Wi and the selected bit line Bj for read or write operation as described above.
The variation in tunneling current through the selected magnetic memory cell is faint. As the array size is increased and the number of the memory cells connected to the single word line or the single bit line is increased, a parasitic capacitance between the selected word and bit lines is increased because the insulating non-magnetic layer sandwiched by the ferromagnetic free and pinned layers is extremely thin, for example, about 1.5 nanometers. The increase in the parasitic capacitance causes an increase in response delay time in read operation, whereby an access time becomes long.
In order to realize a high speed access to the magnetic memory cells, it is desirable to limit the number of the magnetic memory cells connected to the single word line or the single bit line. This provides a limitation to the cell array scale.
Even if the increase in the access time to the memory cells is accepted, then further problem is raised with the increase in the resistances of the word and bit lines, so that the resistances of the word and bit lines become so large as not ignorable with reference to the resistance of the insulating non-magnetic layer sandwiched by the ferromagnetic free and pinned layers, thereby making it difficult to detect the inherently faint variation of the tunneling current.
In the above circumstances, the development of a novel non-volatile semiconductor memory device free from the above problems is desirable.
Accordingly, it is an object of the present invention to provide a novel non-volatile semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel non-volatile semiconductor memory device having a large scale array of magnetic memory cells with reduced parasitic capacitances of word and bit lines.
It is a still further object of the present invention to provide a novel non-volatile semiconductor memory device allowing high speed access to the magnetic memory cells.
It is yet a further object of the present invention to provide a novel MRAM free from the above problems.
It is yet a further object of the present invention to provide a novel MRAM having a large scale array of magnetic memory cells with reduced parasitic capacitances of word and bit lines.
It is yet a further object of the present invention to provide a novel MRAM allowing high speed access to the magnetic memory cells.
It is yet a further object of the present invention to provide a novel magnetic memory cell array free from the above problems.
It is yet a further object of the present invention to provide a novel magnetic memory cell array having a large scale with reduced parasitic capacitances of word and bit lines.
It is yet a further object of the present invention to provide a novel magnetic memory cell array allowing high speed access to the magnetic memory cells.
The present invention provides a memory cell array structure comprising: a plurality of cell array blocks aligned in matrix in both the row and column directions, and each of the cell array blocks including a plurality of magnetic memory cells; a plurality of main word lines extending in a row direction, and each of the main word lines being connected through sub-word switching devices to the same number of sub-word lines as a first number of the cell array blocks aligned in the row direction, and each of the sub-word lines being connected to at least one of the magnetic memory cells; and a plurality of main bit lines extending in a column direction, and each of the main bit lines being connected through sub-bit switching devices to the same number of sub-bit lines as a second number of the cell array blocks aligned in the column direction, and each of the sub-bit lines being connected to at least one of the magnetic memory cells.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.